受新加坡某大型半导体公司委托，招聘赴新加坡半导体IC Design--CAD Digital Engineer (DE)
工作地点：新加坡
* Must have experience in P&R tech file development, Tech file writing. Solid experience on physical part of Digital Place & Route Flows
Required Experience:
At least 2-4 year of experience with digital PNR flow and implementation
Expertise in full backend ASIC implementation flow including chip floor-plan, placement, timing closure, CTS, routing, & ECO
Hands on experience in creating router tech file for EDA tools.
Experience with Parasitic tech file generation and validation like Captables, TLUPLUS
Hands on experience with 180nm, 130nm, 90nm, 65nm, 45nm, 32/28nm & 22/20nm technologies in the area of yield & routability.
Expertise in sign-off DRC and LVS
Able to debug flow/design issues, work around tool bugs, and write scripts to solve problems with the design or the tool.
Prefer to have:
Taped out experience of designs using both Cadence and Synopsys tools
Strong scripting experience in Perl, TCL, Python, and Make
Familiarity with advanced process technologies, including on-chip variation effects, DFM, device and interconnect modeling, and complex design rules

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